Information signal recording and playback method and apparatus therefor

ABSTRACT

In an apparatus for recording and reproducing a burst-like digital information signal, a method capable of predicting the time of occurrence of a header indicating the head of the first data of a digital information signal during its reproduction from a recording medium. The digital signal includes a plurality of data blocks each including a header indicative of the head of the block, and each header includes the address of the block. During recording of the digital signal on the recording medium, a plurality of headers which are substantially the same as the headers of the data blocks and including addresses having given relations with the addresses of the data blocks are inserted in a clock regenerating signal recorded before the digital signal for regenerating the clocks for the signal. The headers are inserted at a period equal to the length of each data block so as to be synchronized with the headers of the data blocks.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method and apparatus forrecording and playing back PCM signals from a magnetic tape and moreparticularly to a synchronization protecting apparatus well suited forrecording and playing back a PCM sound when the overlap area of an 8 mmvideo tape recorder is expanded.

[0002] In the past, the track format 31 of the conventional 8 mm videotape recorder has been determined as shown in FIG. 12. As shown in theFigure, a video signal 34 is recorded on an area 31 V corresponding tothe cylinder head wrapping portion of 185 degrees and a PCM sound signal37 time-base compressed to sterephonic sound data for one field isrecorded on an area 31P overlapping 36-degrees in the direction of thehead scan entering side of the video signal 34. The 36-degree overlaparea 31P includes a scan starting section 39 (a margin section for ahead scan starting point), a preamble 38 (a clock regenerating signalfor clock pull-in purposes), the PCM sound signal 37, a postamble 36 (amargin section during the period of after recording) and a VP guard 35(a guard section between the video signal and the PCM sound signal), andthe PCM sound data 37 begins at the position of 5 degrees from the headscan entering side. Then, the signals 38 to 36 are subjected to biphasemark modulation and recorded on the magnetic tape. With this PCM soundof the conventional 8 mm video tape recorder, the sampling frequency is31.5 kHz and the number of quantization bits is 10. These values areinferior in sound quality as compared with the sampling frequencies of48 kHz and 44.1 kHz and the number of quantization bits or 16 bits whichare the main trends in the field of CD and DAT. However, since the PCMsound whose sampling frequency is 48 kHz and whose number ofquantization bits is 16 has an amount of information which is aboutthree times that of the conventional PCM sound, any attempt to realizesuch amount of information in the same overlap area 31P of 36 degrees aspreviously by utilizing the conventional PCM sound system requires aline recording density of about 3 times the conventional one.

[0003] Thus, the optimization of the correcting codes has been effectedto reduce the line recording density and yet the line recording densityof about 2.5 times has been required. And, in an attempt to realize ahigh-density magnetic recording, a high-performance tape has been usedto optimize the modulation system and yet it has been limited to therecording and playback of the line recording density of about 2 timesthat of the conventional PCM sound.

[0004] Therefore, in order that a PCM sound whose sampling frequency is48 kHz and number of quantization bits is 16 may be realized in an 8 mmvideo tape recorder, there is no alternative but to expand the overlaparea 31P of 36 degrees. FIG. 12 shows a new 8 mm track format 32 inwhich the overlap area is expanded by 5 degrees. By so expanding theoverlap area 32P into a linear audio track which is not used, it ispossible to realize a PCM sound having the sampling frequency of 48 kHzand the number of quantization bits of 16 with a line recording densityof slightly over 2 times the conventional one (see JP-A-1-119966).

[0005] By expanding the overlap area by 5 degrees, it is possible torealize a sound having a sampling frequency of 48 kHz and 16quantization bits in terms of line recording density. However, as shownin FIG. 12, expanding the overlap area by 5 degrees reduces the distancefrom the lower edge of a magnetic tape 10 and hence the head playbackoutput at around the head entry side of the track 32. This is due to thefact that upon the entry of the cylinder head, the lower edge of themagnetic tape 10 is turned up thereby increasing the gap between thehead and the tape. In this way, at around the head entry side the S/Nratio is deteriorated by the reduced playback output and hence the errorrate is deteriorated.

[0006] On the other hand, the vicinity of the head entry side is alsonear to the head of PCM sound data 42 and therefore a burst error tendsto occur. This is due to a synchronization error. The PCM sound data 42has a format 50 such as shown in FIG. 13 and the sound data for onefield is divided into several blocks. Each block is added, as a header51, with a synchronizing signal, ID code (control signal), block addressand parity code as shown in FIG. 3 and they serve important roles suchas the synchronization for converting serial signal data into parallelsignal data in terms of symbols and the generation of the accurate RAMaddress for the sound data in the block. As a result, a measure is takenso that during the period of playback the synchronizing signal and theblock address inthe header 51 are protected by referring to theinformation preceding several blocks thereby reducing the effect due toany desynchronization or block address error. However, there is noinformation to be referred to for the synchronizing signal and the blockaddress in the leading block and the protection is deteriorated. Morespecifically, if an error is caused in the header 51 of the leadingblock, during the data conversion in terms of symbols a synchronizationerror or RAM address error is caused thereby causing a situationequivalent to the occurrence of a burst error of the block length evenif the sound data in the block is correct entirely.

[0007] In this manner, the expansion of the overlap by 5 degreesdeteriorates the playback output at around the head of the track as wellas the error rate. Also, the probability of a synchronization error oraddress error in the leading block is increased and a burst error of theblock length tends to occur. As a result, the probability of generatingsound data by interpolation is increased thus giving rise to a problemof deterioration in the sound quality.

[0008] Disclosed in JP-A-60-247867 is a technique for recording asynchronizing signal pattern in the area of synchronizing clock signalsfor signal playback purposes with a view to preventing suchsynchronization error in the leading block of a track.

SUMMARY OF THE INVENTION

[0009] It is an object of the present invention to provide means forprotecting the synchronizing signal and block address in a header of aleading block.

[0010] Here, let us note a preamble positioned in the head entry side ofPCM sound data. This preamble signal is provided for the reason that aclock regenerating circuit requires a pull-in time of several tens μsfor the regeneration of the normal frequency from the free runningfrequency and usually the minimum recording wave length is recorded inorder to increase the edge component. However, even if the headerincluding the synchronizing signal, etc., is written in the preamble,such information is subjected to the same digital modulation as the datato manage the maximum recording wave length and therefore noconsiderable effect is caused on the pull-in time.

[0011] Thus, the above-mentioned object is accomplished by writing theheader information in the preamble to form a dummy block structure.

[0012] By thus forming the preamble into a dummy block structureincluding the headers, the dummy block performs the same function as theleading data block of the PCM sound data so that the leading data blockof the PCM sound data is enabled to refer to the synchronizing signalsor the block addresses of the preceding blocks so as to provide aneffective protection.

[0013] In accordance with the present invention, by virtue of theexpanded overlap area there is an effect that even if the playbackoutput at around the head scanning starting point is reduced so that theerror rate is deteriorated and an error is caused in the header of theleading data block, it is possible to ensure the protection of thesynchronizing signal, the protection of the block address and thegeneration of an address thereby preventing the occurrence of a bursterror of a length corresponding to the block due to a synchronizationerror or block address error in the leading block.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIGS. 1A, 1B, 1C, 1D, 1E and 1F are diagrams showing basic dataarrangements according to an embodiment of the present invention.

[0015]FIGS. 2A and 2B are diagrams showing basic data arrangements in adata frame according to the embodiment of the invention.

[0016]FIGS. 3, 4 and 5 show respectively the address arrangements indata frames according to the embodiment of the invention.

[0017]FIG. 6 is a basic block diagram of an embodiment of a recordingapparatus according to the invention.

[0018]FIGS. 7A and 7B are flow charts showing operations of the headergenerating circuit of FIG. 6.

[0019]FIGS. 8A, 8B and 8C show examples of the regenerating operationsof a regenerating signal of a digital information signal, with FIG. 8Ashowing an arrangement of the digital information signal, 8B showing aregenerating operation when the synchronizing signal is detected beingin error and 8C showing a regeneration operation when the address isdetected being in error.

[0020]FIG. 9 is a block diagram showing an embodiment of a signalplayback apparatus.

[0021]FIG. 10 is a block diagram showing a basic operation of thesynchronization protecting and demodulating circuit of FIG. 9.

[0022]FIG. 11 is a block diagram showing an embodiment of a recordingand playback apparatus according to the present invention.

[0023]FIG. 12 is a track format diagram showing the track formats on atape.

[0024]FIG. 13 is a diagram showing the data format used in theembodiment of the present invention.

[0025]FIG. 14 is a diagram showing an arrangement of the dummy block.

[0026]FIG. 15 is a data arrangement diagram showing the content of thedummy block.

[0027]FIG. 16 is a modulated waveform diagram showing the modulatedwaveform on the tape.

[0028]FIG. 17 is a block diagram showing the operation of thesynchronization protecting and demodulating circuit of FIG. 11.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The first embodiment of the present invention will now bedescribed. FIGS. 1A, 1B, 1C, 1D, 1E and 1F show the arrangements of datawhen the present invention is applied to a digital information signalwhich is transmitted or recorded in burst form. In FIGS. 1A to 1E,symbol P designates preamble signals 1, D digital signal data 2, Hheaders 3, S synchronizing signals 4, A addresses 5, and PA parity codes126. In the case of a digital information signal which is transmitted orrecorded in burst form, a preamble signal for clock regeneratingpurposes must be recorded in the portion preceding the digitalinformation signal in time. The present invention notes the preamblesignal which is present before the digital information signal. Thedigital information signal is usually formed into a frame including aplurality of data blocks and a header including a synchronizing signal,address, etc., is arranged at the head of each data block. Thesynchronizing signal synchronizes the data block and it also deals withdesynchronization of the block, etc. The address of the data block iswritten as the address and it is utilized for the generation of an RAMaddress during the period of signal processing. In the arrangement ofthe digital signal, the header is written in the data at intervals of agiven time as shown in FIG. 1A.

[0030] Consider now a case where an error is caused in the header inFIG. 1 showing the conventional data arrangement. Firstly, where anerror is caused in any other header than the leading header 3(a) or aheader 3(b), for example, if the header 3(a) has been detected andsynchronization has been established, the synchronous state can bemaintained by utilizing the fact that the headers are written atintervals of the given time and also the value of the RAM address of theheader 3(b) can be accurately predicted due to the fact that the addressof the header 3(a) has been read. However, where an error is caused inthe leading header 3(a), it is impossible to make a confirmativedetermination as to the synchronous state to be referred to or whetherthe error has been caused in the leading header and hence it isimpossible to predict the values of the RAM addresses of the header 3(b)and the following. As a result, the contents of the data becomeerroneous until the accurate header is detected. Thus, as in the case ofFIG. 1B showing a data arrangement according to the first embodiment ofthe present invention, if headers 3 are written in a preamble signal 1such that they are synchronized with the headers in the data, so far asany header in the preamble signal 1 has been detected, it is possible tomaintain the synchronous state and accurately predict the values of theRAM addresses even if an error is caused in the leading header of thedata. In the case of FIG. 1C where synchronizing signals are written asheaders, if synchronization is established by the synchronizing signalsin the preamble signal 1, the data can be reproduced even if thesynchronizing signal is detected being in error. In the case of FIG. 1Dwhere a synchronizing signal and an address are written as each header,if values which allow prediction of the value of the leading address ofthe data are written as the addresses in the preamble, not only an errorin the synchronizing signal can be dealt with but also the position ofthe leading header 3(a) of the data blocks can be predicted. Inaddition, the fact that the address 5 is written to succeed thesynchronizing signal 4 can be utilized such that even if the samewaveform as the synchronizing signal is generated at a place other thanthe position of the proper synchronizing signal in the preamble signalduring the regenerating operation, by determining for example whetherthe waveform is accompanied with the address signal, it is possible todetermine whether the waveform is the regular synchronizing signal.

[0031] Referring to FIG. 1E where an address parity code 126 is written,in addition to a synchronizing signal 4 and an address 5, as each headerso that even if the address is reproduced erroneously, the error in theaddress can be corrected by the parity check. The headers 3 can bewritten at intervals of a given time in a preamble 1, and in theembodiment of FIG. 1E they are written at a period which is two timesthe data block length. The same modulation system as the data can beused on the headers in the preamble to manage the maximum recording wavelength and thus no considerable effect is caused on the time for clockregeneration. It is to be noted that while the preamble signal for PCMsignal reproducing purposes includes generally a clock regeneratingsignal for clock regenerating purposes, in the case of regenerating forexample a carrier-suppressed signal as in the S-VHS system, in order toregenerate the same carrier as the recording side on the reproducingside, during the recording a carrier regenerating signal can be recordedalong with a clock regenerating signal so as to insert the previouslymentioned headers into these signals.

[0032] The second embodiment of the invention will now be described.FIG. 2B is a diagram showing a data arrangement obtained when thepresent invention is applied to a digital information signal of the dataframe structure such as shown in FIG. 2A which is transmitted orrecorded in burst form. Where the digital signal data has the framestructure as shown in FIGS. 2A and 2B, a preamble 1 can be formed into ablock structure so that by recording a dummy header 7 of the samestructure as the headers of a data frame 6 along with a dummy block 9 asshown in FIG. 2B, during the reproduction the same effects as thepreviously mentioned first embodiment can be obtained with respect tothe synchronization and the generation of RAM addresses. Also, whenprotecting the synchronizing signal and the address during thereproduction, the dummy header 7 is the same in structure as the header3 of the data frame 6 and therefore there is no need to newly add anyspecial protective method. Then, as the value of the dummy data 8 in thedummy block 9, data is written which makes a recording or transmittingwaveform advantageous for clock regeneration when using the samemodulation as the data frame 6.

[0033] Specific exemplary methods of designating block addresses 11 ofthe dummy block 9 and the data blocks will now be described. FIGS. 3 to5 show the methods of designating the block addresses 11 of the dummyblock 9 when the leading address of the data blocks is n. In theFigures, symbol S designates synchronizing signals, I ID codes (controlsignals), BA block addresses, P parity codes, DD dummy data and D data.In the case of FIG. 3, the block addresses of the dummy block 9 arerespectively designated as n−6, n−5, n−4, n−3, - - - with respect to theleading address n of the data blocks, so that if any one of the blockaddresses of the dummy block 9 is reproduced as the accurate address, itis possible to determine the number of blocks by which this addressprecedes the leading address n so that even if all of the followingblock addresses of the dummy block cannot be reproduced, the position ofthe leading address n of the data blocks can be predicted accurately.FIG. 4 shows a case where addresses which are not present in the blockaddresses 11 of the data frame 6 are used as the block addresses of thedummy block 9. This system has the advantage of easily distinguishingthe dummy block from the data blocks.

[0034]FIG. 5 shows an embodiment of the method of designating the blockaddresses 11 which ensures matching between the addresses and thecontrol signals when there are given relations therebetween. There arecases where the control signals have different control contents inrelation with the addresses so as to perform more complicated controls.For instance, there is an instance where the control signal of a blockhaving an odd-numbered address performs a control designated as “A” andthe control signal of a block having an even-numbered address performs acontrol designated as “B”. Thus, in the present embodiment, if mrepresents the number of blocks in the data frame 6 and k the number ofheaders in the dummy block 9, by designating the leading to the lastblock addresses as n+m−k, n+m−(k−1), - - - n+m−1 or n+m−(k−1),n+m−(k−2), - - -, n+m, the previously mentioned matching between theaddresses and the control signals can be ensured.

[0035] In this way, by using as the block addresses of the dummy block 9such values capable of predicting the value of the leading address n ofthe data blocks in the data frame 6 in accordance with a certain rule,it is possible to generate an accurate address even if an error iscaused in the header of the leading data block.

[0036] The third embodiment of the invention will now be described. FIG.6 is a basic block diagram of an embodiment of a recording apparatus forrecording a digital information signal on a magnetic tape in accordancewith the present invention. The digital information signal applied to adata input terminal 201 is applied to a signal processing circuit 202.The signal processing circuit 202 performs interleaving of the data, thegeneration and addition of error correcting codes, etc., and datagenerating circuit 203 generates data which is modulated into a clockregenerating signal after the modulation. The outputs of the signalprocessing circuit 202 and the data generating circuit 203 are appliedto a data selector circuit 204 so that the input from the datagenerating circuit 203 is selected and generated during the interval ofthe clock regenerating signal and the input from the signal processingcircuit 202 is selected and generated during the interval of the digitalinformation signal. A header generating circuit 205 generatessynchronizing signals, addresses, control signals and error detectingsignals. As regards the method of designation used in the generation ofaddresses, where the designation of addresses is to be effected as forexample in the case of the embodiment of FIG. 3, if n represents theleading address, the addresses are designated in time sequence as n,n+1, n+2, - - - in the interval for recording the digital informationsignal, whereas in the interval for recording the clock regeneratingsignal, the generation of addresses is effected in the form of n−k, - --, n−2, n−1 if the number of blocks in the clock regenerating signalinterval is represented by k.

[0037] These operations will be described in greater detail in referenceto the flow charts of FIGS. 7A and 7B. The number of symbols in eachdata block is S (block 230). The first generated address value n−k isproduced first (processing block 231). A processing block 232 generatesa header including an address formed by the generated address, a controlsignal formed by control data and an error detecting signal (paritycheck) formed by logically combining the address and the control signal.Then, a decision block 233 makes a decision on the address so that atransfer is made to a processing block 234 where clock regenerating datais added to the header (when address<n is YES) and a transfer is made toa processing block 235 where PCM data is added to the header (whenaddress<n is NO).

[0038] Each header is formed by a total of four symbols (S-4), that is,it is formed by a sychronizing signal (which is added by a processingblock 236 described later), a control signal, an address and a paritycheck which are each formed by a single symbol, and the processing block234 adds to the S-4 symbols data which is useful for clock regeneratingpurposes (i.e., data which results in a clock regenerating signal aftermodulation). Similarly, the processing block 235 adds the PCM data andan error correcting code to the S-4 symbols. Finally, the processingblock 236 adds a synchronizing signal as mentioned previously therebycompleting one data block and the data block is modulated and recordedon a magnetic tape (processing block 237).

[0039] Thus, 1 is added to the address value of the data block(processing block 238) to generate the next address, and thereafter thesimilar processing is repeated.

[0040] The operation of recording a carrier suppressed signal as in thecase of the previously mentioned S-VHS system will now be described withreference to FIG. 7B. The operation differs from the processing of FIG.7A in that a synchronizing signal is added in the generation of a header(processing block 250) and that data useful for carrier regeneration andclock regeneration are added by a processing block 251. The data usefulfor carrier regenration and clock regeneration may be such data having awavelength which is two times the minimum recording wave length. Also,it is possible to add the carrier regnerating signal to the front blockand add the clock regenerating signal to the rear block.

[0041] The other processing operations of FIG. 7B are practically thesame as FIG. 7A, and a completed data block is carrier modulated(processing block 252) and recorded.

[0042] The output of the header generating circuit 205, which generatesthe header by the above-mentioned operation, and the output of the dataselector circuit 204 are applied to another selector circuit 206 whichin turn changes its positions at intervals of one data block periodirrespective of the interval of the clock regenerating signal (thesignal from the data generating circuit) and the interval of the digitalinformation signal. The output of the selector circuit 206 is modulatedby a modulator circuit 207 so that the data from the data generatingcircuit 203 is modulated to a clock regenerating signal. The signalmodulated by the modulator circuit 207 is applied to a recording circuit208 so that the signal is written on the magnetic tape thereby writingin the clock regenerating signal the headers of the same structure asthe headers in the digital information signal so as to be synchronizedwith the latter headers.

[0043] An example of a reproducing method according to the presentinvention will now be described as the fourth embodiment. FIGS. 8A, 8Band 8C show examples of an operation performed when the invention isapplied to the reproduction of a digital information signal. FIG. 8Bshows an operation performed when the first synchronizing signal of thedigital information signal is in error. Since the synchronizing signalis reproduced at a given period as shown in the Figure, if only thesingle accurate synchronizing signal is reproduced in the clockregenerating signal interval, due to the reproducing period of thesynchronizing signals being known preliminarily, by using a synchronouscounter which repeats at the period of the synchronizing signals asshown in the Figure, the positions of the synchronizing signals can bedetected in accordance with the count values of the synchronous counter.As a result, even if the leading synchronizing signal of the digitalinformation signal is detected in error, the data can be reproducedaccurately. At this time, the determination of whether the synchronizingsignal is accurate or not is made in such a manner that the controlsignal (ID code), the address and the error detecting signal (paritycode) immediately following the detected synchronizing signal arecalculated and the determination is made on the basis of non-existenceof error. FIG. 8C shows an operation performed when the first address ofthe digital information signal is in error. If at least one accurateaddress is reproduced in the clock regenerating signal interval as shownin the Figure, due to the fact that the reproduction period of thesynchronizing signals is known, even if an error is caused in thefollowing addresses, the address value can be counted up at the givenperiod so that the accurate addresses can be generated even though thefirst address of the digital information signal is in error. At thistime, the determination of whether the address is accurate or not ismade in the same manner as in the case of FIG. 8B, that is, the controlsignal, the address and the error detecting signal are calculated andthe determination is made on the basis of the non-existence of error andthe continuity of the reproduced address.

[0044] By using the above-mentioned reproducing system, even if thefirst synchronizing signal of the digital information signal is inerror, synchronization can be maintained starting from the first data ofthe digital information signal. Also, even if the first address of thedigital information signal is in error, by detecting the accurateaddress in the clock regenerating signal interval, it is possible togenerate the accurate address starting at the first data of the digitalinformation signal.

[0045] The fifth embodiment of the invention will now be described. FIG.9 is a basic block diagram in which the present invention is applied tothe reproduction of a signal including a clock regenerating signal and adigital information signal which are divided in area. The reproducedsignal applied to a reproduced signal input terminal 210 is subjected tosignal amplification and clock regeneration by a regenerating circuit211 and the resulting digital waveform is applied to a synchronizationprotecting and modulating circuit 212. The synchronization protectingand modulating circuit 212 performs the following processing. FIG. 10 isa block diagram showing a basic operation of the synchronizationprotecting and modulating circuit 212. The input reproduced signal isapplied to a synchronizing signal detecting and protecting circuit 218so that the data synchronizing-signal is detected starting from theclock regenerating signal interval and the detected synchronizing signalis checked as to whether it is accurate. If it is determined accurate,the synchronous counter is initialized and the counting is repeated atthe reproduction period of the synchronizing signals, therebymaintaining the accurate synchronization. On the contrary, if it isdetermined inaccurate and there is no preceding accurate synchronizingsignal, the detection of the synchronizing signals is always effected.By thus performing a data synchronizing operation starting from theclock regenerative signal interval, it is possible to maintain thesynchronization of the data even if the first synchronizing signal ofthe digital information signal is in error. The data synchronzed by asynchronizing circuit 219 is demodulated by a demodulator circuit 220 toproduce digital data. Then, the addresses are detected from thedemodulated digital data by an address detecting and protecting circuit221. The detection of the addresses is also started from the clockregenerating signal interval and a decision is made as to whether thedetected address is accurated. If it is determined accurate, the addressis maintained. If it is determined inaccurate, an accurate address isgenerated by using the previously maintained address. By thus performingthe address protecting operation starting from the clock regeneratingsignal interval, it is possible to maintain the proper time sequentialorder of the data even if the first address of the digital informationsignal is in error. The addresses generated by the address detecting andprotecting circuit 221 are applied to a clock regenerating signaldiscriminating circuit 213 of FIG. 9 so that the clock regeneratingsignal and the digital information signal are discriminated from eachother and the clock regenerating signal is deleted by a clockregenerating signal eliminating circuit 214. After the clockregenerating signal has been eliminated, the digital information signalis applied to a signal processing circuit 215 which performs an errorcorrecting process and data interleaving thereby reproducing it as thedigital information signal.

[0046] By thus effecting the protection of the synchronizing signals andthe addresses starting from the interval of the clock regeneratingsignal during the reproduction, it is possible to prevent the occurrenceof a burst error at around the top of the digital information signal dueto the inaccurate first synchronizing signal or address of the digitalinformation signal.

[0047] The sixth embodiment of the invention will now be described. FIG.11 is a basic block diagram of this embodiment in which the invention isapplied to an apparatus for recording a digital information signal inburst form on a magnetic tape and reproducing it, e.g., the PCM sound ofan 8 mm video tape recorder.

[0048] The operation of the recording system will be described first.The analog signal applied through an analog signal sound input terminal101 is quantized at a given sampling frequency by an A/D converter 102thereby converting it to digital signal data in terms of quantizationbits. Data in terms of symbols is generated from the converted digitalsignal data by a symbol generating circuit 103 and a signal processingcircuit 104 generates correcting codes, headers, etc., from the symboldata, thereby producing a format 50 such as shown in FIG. 13. In thecase of the format shown in FIG. 13, the field frequency of video signalis selected 60/1.001 Hz according to the NTSC and it corresponds to thesound data for one field. While the format of this embodiment will bedescribed on the basis of the NTSC system, the present invention issuitably applicable to any other system such as the PAL system.

[0049] The structure of the format 50 includes an array of 110 blockseach including 44 symbols, and a header 51 is provided with asynchronizing signal, ID code (control signal), block address and paritycode resulting from an exclusive OR operation on the ID code and theblock address. Each block is provided with a 4-symbol C₁ code 52, and asingle 4-symbol C₂ code is added to each C2 code system with aninterleave of 5 blocks as shown in FIG. 13 thereby adding a total of 20blocks of C₂ codes 53.

[0050] With the format shown in FIG. 13, the data frame 50 is providedwith a dummy block 60 by a dummy block adding circuit 105 so as to beplaced in a position on the head entry side as shown in FIG. 14. Asshown in FIG. 14, the dummy block 60 is provided with dummy headers 61and each dummy header 61 is provided with a synchronizing signal, IDcode (control signal), block address and parity code as in the case ofthe data block header 51. FIG. 15 shows the header portion in anexpanded form. In the Figure, designated by SYNC are synchronizingsignals, ID ID codes, B.Adr block addresses, and PARITY parity codes.The block addresses of the dummy block 60 represent an application ofthe previously mentioned embodiment shown in FIGS. 3 and 4. At thistime, the synchronizing signal is replaced by a modulated code of “311”(sexadecimal) or “111” (sexadecimal) by a modulator circuit 106 incorrespondence to the preceding modulation pattern. FIG. 16 shows themodulated waveform generated when the leading block of the dummy blockis actually recorded on the tape. The modulated waveform is obtained byfirst converting the data to a modulated code, converting the modulatedcode to a serial data and then subjecting the serial data to NRZIconversion.

[0051] By forming the data 62 in the dummy block into “EB”(sexadecimal), it is converted to “1111111111” (binary) in terms of an8-10 modulated code (see DIGITAL AUDIO TAPE RECORDER SYSTEM DAT JUNE1987 THE DAT Conference, PP. 32, 38).

[0052] By performing the NRZI conversion, it is possible to produce acontinuous modulated waveform of the minimum recording wave length bythe output of the modulator circuit 106.

[0053] In accordance with this embodiment, due to the use of the 8-10modulated code, the modulated waveforms of the other data can be limitedto a wavelength which is 4 times the minimum recording wave length atthe most (i.e., the modulated waveform of sync) and there is practicallyno effect on the pull-in time during the clock regeneration.

[0054] After the dummy block 60 of FIG. 14 has been added in this way,the data frame 50 is modulated by the modulator circuit 106 and it isthen applied to a recording circuit 107. In this case, the video signalapplied through a video input terminal 12 is also processed by arecording video signal processing circuit 108 thereby applying it to therecording circuit 107. The recording circuit 107 distributes the PCMsignal and the video signal to the two heads of a cylinder 109 therebyrecording the signals on a magnetic tape 110 in the form of a new 8 mmtrack format 32 of FIG. 12 in which the overlap area is expanded by 5degrees as compared with the previously mentioned conventional PCMsignal.

[0055] Next, the operation of the playback system will be described. Themagnetic record pattern on the magnetic tape 110 is detected by the twoheads of the cylinder 109 and the reproduced signal is applied to aplayback circuit 111. The playback circuit 111 amplifies and divides thesignal into the PCM signal and the video signal according to therecording areas so that the video signal is applied to a reproducedvideo signal processing circuit 112 and the PCM signal is subjected toclock regeneration thereby applying the signal as serial digital signaldata, along with the regenerative clocks, to a synchronizationprotecting and modulating circuit 113. The synchronization protectingand modulating circuit 113 performs the protection and demodulation ofthe synchronizing signals and the blocks addresses. FIG. 17 is a blockdiagram showing the overall operation of the synchronization protectingand demodulating circuit 113 and a dummy block eliminating circuit 114and the operation will now be described.

[0056] The reproduced data and the regenerated clocks are applied to ashift register 80 which converts the input data to a parallel signal anda synchronizing signal detecting circuit 82 detects the synchronizingsignals. After the synchronizing signals have been detected, thedetected signals are applied to a synchronous counter 83 through adetection window generating circuit 84 thereby providing synchronizationin terms of symbols. A demodulating and synchronizing circuit 81 effectsthe synchronization and demodulation in terms of symbols. In this case,the protection of the synchronizing signals is effected by asynchronization and address protecting circuit 90 and the detectionwindow generating circuit 84. The basic operation utilizes the fact thatthe synchronizing signals are reproduced at the rate of one for everyblock at intervals of the given time. In other words, after the regularsynchronizing signal has been detected for the first time, thesynchronizing signals are detected only for the detection window atintervals of a certain time, whereas when the regular synchronizingsignal is not detected, the protection of synchronization (themaintenance of the preceding synchronous state) is effected for theinterval of the several blocks. Thereafter, if any synchronizing signalis not detected, a search is made again for the regular synchronizingsignal. In this case, the normality of the synchronizing signal isdetermined in accordance with the normality of the block address. Byeffecting the synchronization protection by such procedure, errors inthe synchronizing signals and demodualtion of the reproduced signal canbe dealt with. The thus synchronized symbol data is written in an RAM 93through a data bus 94.

[0057] The protection of the addresses during the writing into the RAM93 will now be described. The block addresses correspond to theaddresses in the RAM 93 and thus if any error is caused in the addressesso that the data is written at the inaccurate RAM address, the timesequential order of the reproduced signal is deranged and it leads toinaccuracy of the blocks on the whole. Therefore, the protection of theaddresses must be effected effectively. In the apparatus of theembodiment shown in FIG. 17, the normality of the addresses isdetermined in such a manner that the provision of protection isdetermined in accordance with the results of {circle over (1)} a paritycheck circuit 87 for checking the parity of the header 51, {circle over(2)} an address continuity check circuit 88 and {circle over (3)} areproduced address≦decoded address check circuit 89. In other words,only those addresses which have passed the above checks {circle over(1)} to {circle over (3)} are determined as being accurate and thereproduced addresses are used as the RAM addresses. If the reproducedaddress is in error so that the address fails to pass these checks{circle over (1)} to {circle over (3)}, the address protection isperformed and the count value from the accurate address preceding theoccurrence of the inaccurate reproduced address is used as the RAMaddress.

[0058] By providing such address protection, it is possible to generatea highly reliable RAM addresses even if any block address, ID code(control signal) or parity code of the header is detected as being inerror.

[0059] Let us consider for purposes of comparison the reproduction ofthe conventional data format which has not been provided with the dummyblock. Consider first a case where during the synchronization thesynchronizing signal of the leading block is in error so that thesynchronizing signal cannot be detected by the synchronizing signaldetecting circuit 82. In this case, since the error is in the leadingblock so that there is no synchronization to be referred to, nosynchronization protection can be provided. Thus, the synchronization interms of symbols cannot be provided so that all the data are in erroruntil the normal synchronizing signal is detected next.

[0060] Next, considering a case where the block address of the leadingblock is in error, then there exists no accurate address preceding theoccurrence of the error and thus the protection cannot be effected.Also, it is impossible to show the number of this block in the sequence.As a result, the whole block is considered to be in error and a “0” iswritten in the address of the RAM 93.

[0061] Thus, where errors are caused in the header of the leading block,it is difficult to protect the leading synchronizing signal and theleading block address and the provided protection, if any, will be lesseffective one using an area signal or the like. However, by adding thedummy block 60 shown in FIG. 14 to the data frame 50 as in theembodiment of the present invention, although the leading synchronizingsignal of the data block is in error, if the normal synchronizing signalcan be detected during the reproduction of the several blocks of thedummy block 60, there is no danger of causing a burst error of a lengthcorresponding to the block due to the synchronization error in theleading data block.

[0062] It is to be noted that even if the leading synchronizing signalof the dummy headers 61 is in error, this only causes the leading blockof the dummy block 60 to be in error.

[0063] Also, where the leading address of the data blocks is in error,by designating the block addresses in the headers of the dummy block asshown in FIG. 5 so as to permit the prediction of the position of theleading data block, the data of this block can be written in theaccurate address of the RAM 93. Also, although the leading address andthe block address of the dummy block are simultaneously in error, if thenormal block address is detected during the reproduction of the severalblocks of the dummy block 60, in accordance with the time-like countvalue from the detected block address the address protection can beeffected even if an address error is caused in the leading data blockand the data block can similarly be written in the accurate address ofthe RAM 93. It is to be noted that even if the address error is causedin the dummy block as mentioned above, this portion is a dummy andtherefore no inconvenience is caused.

[0064] It is to be noted that where the accurate block address isdetected from the dummy block, while a processing is required such thatthe dummy data of the dummy block is not written in the RAM 93, theblock address of the dummy block has a value which does not exist in theaddresses of the data blocks and therefore it can be easilydiscriminated by a dummy block discriminating circuit 86. Also, even ifthe dummy data is written in the RAM 93, it is only necessary to performa signal processing such that the RAM address in question is not used.Also, the control information corresponding to the control signals (IDcodes) of the data frame are written in the control signals (ID codes)of the dummy block according to the block addresses.

[0065] Let us now consider the reproduction of PCM sound from an 8 mmvideo tape recorder which records and plays back the previouslymentioned, 16-bit PCM sound. Where the conventional data frame providedwith no dummy block 60 such as shown in FIG. 13 is reproduced, bursterrors of the block length are caused until the normal synchronizingsignal is next detected from the leading data block as mentionedpreviously. Thus, since the top of the PCM sound data 42 comes closer tothe lower edge of the tape due to the expansion of the overlap area asshown in FIG. 12, when the cylinder heads 9 come in, the tape 10 isturned up thereby reducing the reproduced output due to the effect ofthe increased gap between the tape 10 and the heads 9. As a result, theerror rate is deteriorated at around the head of the PCM sound data 42and this increases the probability of failing to detect thesynchronizing signal of the leading data block. Therefore, theprobability of causing a burst error of the block length from theleading data block is increased and hence the probability of generatingthe sound by interpolation of the data is increased, thus causingdeterioration of the sound quality.

[0066] Therefore, the dummy block 60 is added to the data frame 50 inthe previously mentioned manner.

[0067] By applying the method and apparatus of the present embodiment toa 8 mm video tape recorder which records and reproduces such PCM sound,even if errors are caused in the leading data block during the soundreproduction, it is possible to provide protection for the synchronizingsignal and the block address thereby reducing the probability of causinga burst error of the block length due to a synchronization error or RAMaddress error. In other words, when a synchronization error or RAMaddress error is caused in the leading data block of the data frameprovided with the dummy block, this means a case where errors are causedin all the headers 61 of the dummy block 60 and its probability isextremely small.

[0068] In this way, the data written in the RAM 93 is subjected to errordetection and processing of the ID codes (control signals) by a signalprocessing circuit 115 and a symbol composing circuit 116 composes worddata of a given number of quantization bits from the symbol data. Then,a D/A converter 117 converts the digital signal data to analog signaldata and a sound signal is generated from a sound output terminal 118.

[0069] While the embodiments of the recording and playback apparatusaccording to the invention have been described as applied to an 8 mmvideo tape recorder with PCM sound to show its effects, the recordingand playback apparatus of this invention is not limited to the 8 mmvideo tape recorder and it is suitably applicable to apparatus of thetype employing cylinder heads to record a digital signal in burst formon a magnetic recording medium, such as, a video tape recorder and otherapparatus for recording and reproducing video signals and PCM soundsignals, apparatus for recording video signals themselves in PCM form,and apparatus for recording only sound signals in PCM form such as aDAT.

1. An information signal recording method comprising the steps of:recording a burst-like digital information signal including a pluralityof first data-head indicative information arranged at a predeterminedperiod, each of said first information including a synchronizing signal,address, control signal and error detecting signal, and a clockregenerating signal for regenerating clocks for said digital informationsignal on separate areas of a magnetic recording medium by a cylinderhead; generating a plurality of second data-head indictive informationof the same structure as said first data-head indicative information;and applying said second data-head indicative information at apredetermined period to said clock regenerating signal so as to besynchronized with said first data-head indicative information.
 2. Amethod according to claim 1, wherein said digital information signalincludes a plurality of data blocks each including one of said firstdata-head indicative information and main information, said plurality ofdata blocks forming a data frame, and wherein said second data-headindicative information are inserted at a period equal to a length ofeach of said data blocks in said clock regenerating signal.
 3. A methodaccording to claim 2, wherein values of the addresses of said seconddata-head information in said clock regenerating signal are recorded ina manner that a value of the address in the first data-head indicativeinformation of first one of said data blocks is predictable inaccordance with a predetermined rule.
 4. A method according to claim 3,wherein the values of the addresses of said second data-head indicativeinformation in said clock regenerating signal are designated as n−k,n−(k−1), n−(k−2), - - -, n−1, with n representing the value of theaddress of the first data-head indicative information of the first datablock of said digital information signal, and k representing the numberof said second data-head indicative information in said clockregenerating signal.
 5. A method according to claim 3, wherein thevalues of the addresses of said second data-head indicative informationin said clock regenerating signal are set to values which are notassigned to the addresses of said first data-head indicative informationin said digital information signal.
 6. A method according to claim 3,wherein the values of the addresses of said second data-head indicativeinformation in said clock regenerating signal are selected in a mannerthat the rearward addresses in said data frame are designated as n+m−k,n+m−(k−1), n+m−(k−2), - - -, n+m−1, with n representing the value of theaddress of the first data-head indicative information of said first datablock in said digital information signal, m representing the number ofsaid data blocks in said data frame, and k representing the number ofsaid second data-head indicative information in said clock regeneratingsignal.
 7. An information signal recording apparatus for respectivelyrecording a burst-like digital information signal including a pluralityof first data-head indicative headers arranged at a predeterminedperiod, each of said headers including a synchronizing signal, address,control signal and error detecting signal for data, a clock regeneratingsignal for regenerating clocks for said digital information signal onseparate areas of a magnetic recording medium by a cylinder head, saidapparatus comprising: signal processing means for interleaving an inputdata and generating and adding error detecting codes to said input data;data generating means for generating data which has a waveformadvantageous for clock regeneration when modulated by the samemodulation system as used during the recording of said digitalinformation signal; first selector means for selecting an output fromsaid data generating means during an interval of said clock regeneratingsignal and selecting an output from said signal processing circuitduring an interval of said digital information signal; header generatingmeans for generating addresses enabling prediction of a time ofoccurrence of first one of said first data-head indicative informationduring the interval of said clock regenerating signal where a pluralityof second data-head indicative headers of the same structure as saidfirst data-head indicative headers are generated and for generatingaddresses of a time sequential order during the interval of said digitalinformation signal; second selector means for effecting switchingbetween the outputs of said header generating circuit and said firstselector means during the interval of said clock regenerating signal andthe interval of said digital information signal, respectively;modulating means for modulating the output of said second selectormeans; and recording means for recording the modulated signal from saidmodulating means.
 8. An information signal playback method for detectinga magnetic record pattern including a clock regenerating signal and adigital information signal which are respectively recorded on separateareas of a magnetic tape by a cylinder head and regenerating clocks inaccordance with said detected clock regenerating signal therebyreproducing said digital information signal, said method comprising thesteps of: detecting data synchronizing signals starting from an intervalof said clock regenerating signal to determine the normality of eachsaid detected synchronizing signal to protect an existing synchronousstate when the same is determined accurate; detecting addresses startingfrom the interval of said clock generating signal to determine thenormality of each said detected address and protect the same when thesame is determined accurate to predict a time of occurrence of firstdata-head indicative information including a data synchronizing signal,address, control signal and error detecting signal for first one of aplurality of data blocks of said digital information signal; anddiscriminating said clock regenerating signal and said digitalinformation signal from each other in response to the detection of saidaccurate address.
 9. An information signal playback apparatus fordetecting a magnetic record pattern including a clock regeneratingsignal and a digital information signal which are respectively recordedon separate areas on a magnetic tape by a cylinder head and regeneratingclocks in accordance with said detected clock regenerating signalthereby reproducing said digital information signal, said apparatuscomprising: synchronizing signal detecting means for detecting datasynchronizing signals during an interval of said clock regeneratingsignal; synchronization discriminating means for determining whethereach said synchronizing signal detected by said synchronizing signaldetecting means is accurate; synchronous counter means adapted to beinitialized by each said synchronizing signal determined accurate bysaid synchronization discriminating means to repeat counting at asynchronizing signal reproduction period to maintain an accuratesynchronous state; demodulating means for demodulating data; addressdetecting means for detecting addresses of said data during the intervalof said clock regenerating signal; address discriminating means fordetermining whether each said address detected by said address detectingmeans is accurate; address protecting means whereby each said addressdetermined accurate by said address discriminating means is maintained,and an accurate address is generated from a previously maintainedaddress when each said address is determined as being in error by saidaddress discriminating means; clock regenerating signal discriminatingmeans for discriminating said clock regenerating signal and said digitalinformation signal in response to the detection of each said accurateaddress; clock regenerating signal eliminating means responsive to saidclock regenerating signal discriminating means to delete said clockregenerating signal; and signal processing means for performing errorcorrecting processing and data interleaving of said digital informationsignal.
 10. An information signal recording and playback method forrespectively recording a burst-like digital information signal includinga plurality of first data-head indicative information arranged at apredetermined period, each of said first information including asynchronizing signal, address, control signal and error detectingsignal, and a clock regenerating signal for regenerating clocks for saiddigital information signal on separate areas of a magnetic recordingmedium by a cylinder head and for detecting said recorded magneticrecord pattern by said cylinder head and regenerating said clocks inaccordance with said detected clock regenerating signal therebyreproducing said digital information signal, said method comprising thesteps of: forming in said clock regenerating signal a plurality ofsecond data-head indicative information of the same structure as saidfirst data-head indicative information, said digital information signalincluding a data frame including a plurality of data blocks each thereofbeing formed by one of said first information and main information;applying said second data-head indicative information at a predeterminedperiod equal to the length of each of said data blocks to said clockregenerating signal so as to be synchronized with said first data-headindicative information; recording values of the addresses of said seconddata-head indicative information in said clock regenerating signal insuch a manner that a value of the address of said first data-headindicative information in first one of said data blocks is predictablein accordance with a predetermined rule; detecting during reproductionsaid data synchronizing signals starting from an interval of said clockregenerating signal to discriminate the normality of each said detectedsynchronizing signal and thereby to protect an existing synchronousstate when the same is determined to be accurate; detecting saidaddresses starting from the interval of said clock regenerating signalto discriminate the normality of each said detected address whereby wheneach said detected address is determined accurate, said address isprotected to predict a time of occurrence of first one of said firstdata-head indicative information of said digital information signal; anddiscriminating said clock regenerating signal and said digitalinformation signal from each other in response to the detection of saidaccurate address.
 11. A method according to claim 10, wherein values ofthe addresses of said second data-head indicative information in saidclock regenerating signal are designated as n−k, n−(k−1), n−(k−2), - --, n−1, with n representing the value of the address of said firstdata-head indicative information of first one of said data blocks insaid clock regenerating signal, and k representing the number of saidsecond data-head indicative information in said clock regeneratingsignal.
 12. A method according to claim 16, wherein the values of theaddresses of said second data-head indicative information in said clockregenerating signal are set to values which are not assigned to theaddresses of said first data-head indicative information in said digitalinformation signal.
 13. An information signal recording and playbackappratus for respectively recording a burst-like digital informationsignal including a plurality of first data-head indicative headersarranged at a predetermined period, each of said first headers includinga synchronizing signal, address, control signal and error detectingsignal for data, and a clock regenerating signal for regenerating clocksfor said digital information signal on separate areas of a magneticrecording medium by a cylinder head and for detecting said recordedmagnetic record pattern by said cylinder head to regenerate said clocksin accordance with said detected clock regenerating signal therebyreproducing said digital information signal, said apparatus comprising:signal processing means for interleaving an input data and generatingand adding error detecting codes to said input data, data generatingmeans for generating data which results in a waveform advantageous forclock regeneration when the same is modulated by the same modulationsystem as used during recording of said digital information signal;first selector means for selecting an output of said data generatingcircuit during an interval of said clock regenerating circuit andselecting an output from said signal processing means during an intervalof said digital information signal; header generating means forgenerating addresses enabling prediction of a time of occurrence offirst one of said first data-head indicative headers during the intervalof said clock regenerating signal where a plurality of second data-headindicative information of the same structure as said first data-headindicative information are generated and for generating addresses of atime sequential order during the interval of said digital informationsignal; second selector means for effecting switching between the outputof the header generating means and the output of said first selectormeans at a predetermined period during the interval of said clockregnerating signal and the interval of said digital information signal,respectively; modulating means for modulating the output of said secondselector means; recording means for recording the signal modulated bysaid modulating means; synchronizing signal detecting means fordetecting said data synchronizing signals starting from the interval ofsaid clock regenerating signal; synchronization discriminating means todetermine whether each said detected synchronizing signal is accurate;synchronous counter means adapted to be initialized by said synchronizedsignal determined accurate by said synchronization discriminating meansto repeat counting at a synchronizing signal reproducing period tomaintain an accurate synchronous state; demodulating means fordemodulating said data; address detecting means for detecting theaddresses of said data starting from the interval of said clockregenerating signal; address discriminating means for determiningwhether each said address detected by said address detecting means isaccurate; address protecting means for maintaining each said addressdetermined accurate by said address discriminating means and forgenerating an accurate address from a previously maintained address whensaid address discriminating means determines that each said detectedaddress is being in error; clock regenerating signal discriminatingmeans for discriminating said clock regenerating signal and said digitalinformation signal from each other in response to the detection of saidaccurate address; clock regenerating signal eliminating means responsiveto said clock regenerating signal discriminating means to delete saidclock regenerating signal; and signal processing means for performingerror correcting process and data interleaving on said digitalinformation signal.
 14. An information signal recording methodcomprising the steps of: recording a burst-like digital informationsignal including a plurality of data blocks each including firstdata-head indicative information and main information, each of saidfirst information including at least a synchronizing signal and addressfor data, and a clock regenerating signal for regenerating clocks forsaid digital information signal on separate areas of a recording mediumby a cylinder head; forming a plurality of second data-head indicativeinformation each including at least synchronizing signal identifyingcode; and inserting said plurality of second data-head indicativeinformation at a period equal to the length of each of said data blocksin said clock regenerating signal.
 15. An information signal recordingmethod comprising the steps of: recording respectively a burst-likedigital information signal including a plurality of data blocks eachincluding first data-head indicative information and main information,each of said first information including a synchronizing signal andaddress, a carrier regenerating signal for carrier regeneration servingas a signal for regenerating said digital information signal, and aclock regenerating signal for regenerating clocks on separate areas of amagnetic recording medium by a cylinder head; generating a plurality ofsecond data-head indicative information of the same structure as saidfirst data-head indicative information; and inserting said seconddata-head indicative information at a period equal to the length of eachof said data blocks in said carrier regenerating signal and said clockregenerating signal.